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HT45B0F spi-to-uart bridge block diagram rev. 1.00 1 june 7, 2011 features operating voltage f clki = 12mhz: 2.0v~5.5v f clki = 16mhz: 2.7v~5.5v f clki = 20mhz: 4.5v~5.5v glueless slave spi interface to holtek s mcu full-duplex, universal asynchronous receiver and transmitter (uart) communication 8 or 9 bit character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect address detect interrupt - last character bit=1 transmitter and receiver enabled independently 4-byte deep fifo receiver data buffer transmit and receive multiple interrupt generation sources: transmitter empty transmitter idle receiver full receiver overrun address mode detect tx pin is high impedance when the uart transmit module is disabled rx pin is high impedance when the uart receive module is disabled cmos clock input, clki, up to 20mhz at 5v operating voltage 16-pin nsop package general description the HT45B0F is microcontroller peripheral device to im - plement spi-to-uart data conversions. the uart module can operate in full-duplex mode with an interrupt output capability to the host microcontroller. possible application could include data communication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and bat- tery operated devices, factory automation and process control to name but a few.

pin assignment pin description pin name i/o description sdi i serial i/o data input sdi is high impedance when scs = high sdo o serial i/o data output. sdo is high impedance when scs = high sck i serial i/o clock input sck is high impedance when scs = high scs i serial i/o chip select input, active low scs has an internal pull-high resistor. clki i external clock input int o interrupt output (cmos output structure). connected to the mcu s external interrupt input rx i uart rx pin if uarten = 1 and rxen = 1, then rx is the uart serial data input if uarte n=0or rxen = 0, then rx is high impedance tx o uart tx pin if uarten = 1 and txen = 1, then tx is the uart serial data output if uarte n=0or txen = 0, then tx is high impedance vdd positive power supply vss negative power supply, ground nc no connection absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature .......................... 50 c to +150c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature......................... 40 cto+85 c i ol total ................................................................35ma i oh total.............................................................. 35ma total power dissipation .....................................135mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT45B0F rev. 1.00 2 june 7, 2011

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d.c. characteristics ta=25 c sym - bol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f clki = 12mhz 2.0 5.5 v f clki = 16mhz 2.7 5.5 v f clki = 20mhz 4.5 5.5 v i dd1 operating current (spi enabled, uart disabled) 2.0v f clki =12mhz, sck=f clki /4, output no load 0.8 ma 2.7v f clki =16mhz, sck=f clki /4, output no load 1.0 ma 3.3v 1.5 ma 5.0v 2.0 ma i dd2 operating current (spi enabled, uart enabled) 2.0v f clki =6mhz, sck=f clki /4, output no load 4.0 ma 2.7v 4.5 ma 3.3v f clki =12mhz, sck=f clki /4, output no load 5.0 ma 5.0v 6.0 ma i stb standby current (spi disabled, uart disabled) 2.0v f clki =12mhz, sck=f clki /4, scs =v dd , uarten=0, txen=1, rxen=1, sdi=h, rx=h, output no load 0.6 a 2.7v f clki =16mhz, sck=f clki /4, scs =v dd , uarten=0, txen=1, rxen=1, sdi=h, rx=h, output no load 0.6 a 3.3v 0.6 a 5.0v 0.6 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage for clki 0 0.3v dd v v ih2 input high voltage for clki 0.7v dd v dd v i ol i/o port sink current 2.0v v o =0.1v dd 0.5 1.0 ma 2.7v 1.0 2.0 ma 3.3v 4.0 10.0 ma 5.0v 10.0 25.0 ma i oh i/o port source current 2.0v v o =0.9v dd 0.4 0.8 ma 2.7v 1.0 2.0 ma 3.3v 4.0 5.0 ma 5.0v 5.0 8.0 ma r ph pull-high resistance for scs only 2.0v 30 90 150 k
2.7v 20 60 100 k
3.3v 15 45 75 k
5.0v 10 30 50 k
HT45B0F rev. 1.00 3 june 7, 2011
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd slew rate for por 0.0034 v/ms f clki system clock (external clock input) 2.0v 400 12000 khz 2.7v 400 16000 khz 5.0v 400 20000 khz t cp sck period (t ch +t cl ) 2.0v 83.3 ns 2.7v 62.5 ns 3.0v 62.5 ns 5.0v 50.0 ns t ch sck high time 2.0v 37 ns 2.7v 28 ns 3.0v 28 ns 5.0v 22 ns t cl sck low time 2.0v 37 ns 2.7v 28 ns 3.0v 28 ns 5.0v 22 ns t csw scs high pulse width 2.0v 667 ns 2.7v 500 ns 3.0v 500 ns 5.0v 400 ns t css scs to sck setup time 100 ns t csh scs to sck hold time 0 ns t sds sdi to sck setup time 100 ns t sdh sdi to sck hold time 0 ns t r spi output rise time 10 ns t f spi output fall time 10 ns t w spi data output delay time 0 ns HT45B0F rev. 1.00 4 june 7, 2011
HT45B0F rev. 1.00 5 june 7, 2011 functional description the HT45B0F is full-duplex asynchronous serial com - munications uart interface that enables communica - tion with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. all data transmissions and recep - tions between mcu and HT45B0F including uart commands are conducted along this interconnected spi interface. the uart function control is executed by the mcu using its spi master serial interface. the device contains its own independent interrupt which can be used to indicate when a data reception occurs or when a data transmission has terminated. spi interface the mcu communicates with the device via an internal spi interface. the spi interface on this device is com - prised of four signals: scs (spi chip select), sck (spi clock), sdi (serial data input) and sdo (serial data output). the spi master, which is the mcu, asserts scs by pulling it low to start the data transaction cycle. when the first 8 bits of data are transmitted, scs should not return to a high level. instead, scs must remain at a low level until the whole 16-bit data transaction is com - pleted. if scs is de-asserted, that is returned to a high level before the 16-bit data transaction is completed, all data bits will be discarded by the device spi slave. spi timing both read and write operations are conducted along the spi common interface with the following format: write type format: 8-bit command input + 8-bit data input read type format: 8-bit command input + 8-bit data output to initiate a data transaction, the mcu master spi needs to pull scs to a low level first and then also pull sck low. the input data bit on sdi should be stable be - fore the next sck rising edge, as the device will latch the sdi status on the next sck rising edge. regarding the sdo line, the output data bit will be updated on the sck falling edge. the master needs to obtain the line status before the next sck falling edge. there are 16 bits of data transmitted and/or received by the spi interface for each transaction. each transaction consists of a command phase and a data phase. when scs is high, the spi interface is disabled and sdo will be set to a high impedance state. after a complete transaction has been implemented, which requires 16 sck clock cycles, the master needs to set scs to a high level in preparation for the next data transaction. for write operations, the device will begin to execute the command only after it receives a 16-bit serial data se- quence and when the scs has been set high again by the master. for read operations, the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. if necessary, the master can de-assert the scs pin to abort the trans - action at any time which will cause any data transac - tions to be abandoned.
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for example connection
HT45B0F rev. 1.00 6 june 7, 2011 pin interfacing the uart has two pins known as tx and rx. the tx pin is the uart transmitter serial data output pin if the corresponding control bits named uarten in ucr1 register and txen in ucr2 register are set to 1. if the control bit uarten or txen is equal to zero, the tx pin is in the state of high impedance. similarly, the rx pin is the uart receiver serial data input pin if the corre - sponding control bits named uarten and rxen in ucr1 and ucr2 registers are set to 1. if the control bit uarten or rxen is equal to zero, the rx pin is in the state of high impedance. uart data transfer scheme the following block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmitter shift register named tsr from where it will be shifted out, lsb first, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is accessible to the application program, the transmitter shift register is not mapped into the data memory area and is inacces - sible to the application program. data to be received by the uart is accepted on the rx pin, from where it is shifted in, lsb first, to the receiver shift register named rsr at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is accessible to the application program, the re - ceiver shift register is not mapped into the data mem - ory area and is inaccessible to the application program. it should be noted that the actual register for data trans - mission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register physi - cally. this shared register known as the txr/rxr regis - ter is used for both data transmission and data reception. sdo sdi sck scs a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 writing type format: 8-bit command input + 8-bit data input sdo sdi sck scs a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t w reading type format: 8-bit command input + 8-bit data output msb lsb transmitter shift register (tsr) msb lsb receiver shift register (rsr) tx pin rx pin baud rate generator tx register (txr) rx register (rxr) buffer 1 buffer 2 buffer 3 data to be transmitted data received uart data transfer scheme
HT45B0F rev. 1.00 7 june 7, 2011 uart commands there are both read and write commands. for reading and writing to registers both command and address information is contained within a single byte. the format for reading and writing is shown in the following table. command type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read fifo 00000xxx read register 00010a2a1a0 write fifo 00001xxx write register 00011a2a1a0 note: x here stands for don t care uart status and control registers there are six registers associated with the uart function. the usr, ucr1, ucr2 and ucr3 registers control the overall function, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data register. a[2:0] name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h usr 0000 1011 perr nf ferr oerr ridle rxif tidle txif 01h ucr1 0000 0x00 uarten bno pren prt stops txbrk rx8 tx8 02h ucr2 0000 0000 txen rxen brgh adden wake rie tiie teie 03h brg xxxx xxxx brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 04h ucr3 0 urst 05h~ 07h unused reserved uart register summary usr register the usr register is the status register for the uart, which can be read by the application program to determine the present status of the uart. all flags within the usr register are read only. further explanation on each of the flags is given below: bit76543210 name perr nf ferr oerr ridle rxif tidle txif r/wrrrrrrrr por00001011 bit 7 perr : parity error flag 0: no parity error is detected 1: parity error is detected the perr flag is the parity error flag. when this read only flag is 0 , it indicates a parity error has not been detected. when the flag is 1 , it indicates that the parity of the received word is incorrect. this error flag is applicable only if parity mode (odd or even) is selected. the flag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise flag 0: no noise is detected 1: noise is detected the nr flag is the noise flag. when this read only flag is 0 , it indicates no noise condition. when the flag is 1 , it indicates that the uart has detected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of as overrun. the nf flag can be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register.
HT45B0F rev. 1.00 8 june 7, 2011 bit 5 ferr : framing error flag 0: no framing error is detected 1: framing error is detected the ferr flag is the framing error flag. when this read only flag is 0 , it indicates that there is no framing error. when the flag is 1 , it indicates that a framing error has been detected for the current character. the flag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error flag 0: no overrun error is detected 1: overrun error is detected the oerr flag is the overrun error flag which indicates when the receiver buffer has overflowed. when this read only flag is 0 , it indicates that there is no overrun error. when the flag is 1 , it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register. the flag is cleared by a software sequence, which is a read to the status register usr followed by an access to the rxr data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle flag is the receiver status flag. when this read only flag is 0 , it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the flag is 1 , it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif flag is the receive data register status flag. when this read only flag is 0 , it indicates that the rxr read data register is empty. when the flag is 1 , it indicates that the rxr read data register contains new data. when the contents of the shift register are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related flags nf, ferr, and/or perr are set within the same clock cycle. the rxif flag is cleared when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : transmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only flag is 0 ,it indicates that a transmission is in progress. this flag will be set to 1 when the txif flag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1 , the tx pin becomes idle with the pin state in logic high condition. the tidle flag is cleared by reading the usr register with tidle set and then writing to the txr register. the flag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : transmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif flag is the transmit data register empty flag. when this read only flag is 0 ,it indicates that the character is not transferred to the transmitter shift register. when the flag is 1, it indicates that the transmitter shift register has received a character from the txr data register. the txif flag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif flag bit will also be set since the transmit data register is not yet full.
HT45B0F rev. 1.00 9 june 7, 2011 ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the vari - ous options for the uart function such as overall on/off control, parity control, data transfer bit length, etc. further explanation on each of the bits is given below: bit76543210 name uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por000000x0 x unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are in the state of high impedance 1: enable uart. tx and rx pins function as uart pins the uarten bit is the uart enable bit. when this bit is equal to 0 , the uart will be disabled and the rx pin as well as the tx pin will be in the state of high impedance. when the bit is equal to 1 , the uart will be enabled and the tx and rx pins will function as defined by the txen and rxen enable control bits. when the uart is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. in addition, the value of the baud rate counter will be reset. if the uart is disabled, all error and status flags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. when the uart is re-enabled, it will restart in the same configuration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1 , a 9-bit data length format will be selected. if the bit is equal to 0 , then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1 , the parity function will be enabled. if the bit is equal to 0 , then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1 , odd parity type will be selected. if the bit is equal to 0 , then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: two stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to 1 , two stop bits are used. if this bit is equal to 0 , then only one stop bit is used. bit 2 txbrk : transmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the transmit break character bit. when this bit is 0 , there are no break characters and the tx pin operates normally. when the bit is 1 , there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1 , after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset.
HT45B0F rev. 1.00 10 june 7, 2011 bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : transmit data bit 8 for 9-bit data transfer format (write only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the uart control registers and serves several purposes. one of its main func - tions is to control the basic enable/disable operation if the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. further explanation on each of the bits is given below: bit76543210 name txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r w por00001011 bit 7 txen : uart transmitter enable control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the transmitter enable bit. when this bit is equal to 0 , the transmitter will be disabled with any pending data transmissions being aborted. in addition the buffers will be reset. in this situation the tx pin will be in the state of high impedance. if the txen bit is equal to 1 and the uarten bit is also equal to 1 , the transmitter will be enabled and the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. if this situation occurs, the tx pin will be in the state of high impedance. bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to 0 , the receiver will be disabled with any pending data receptions being aborted. in addition the receive buffers will be reset. in this situation the rx pin will be in the state of high impedance. if the rxen bit is equal to 1 and the uarten bit is also equal to 1 , the receiver will be enabled and the rx pin will be controlled by the uart. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be in the state of high impedance. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uart. if this bit is equal to 1 , the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bit named adden is the address detect function enable control bit. when this bit is equal to 1 , the address detect function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1, then the received word will be identified as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of bno. if the address bit known as the 8th or 9th bit of the received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded.
HT45B0F rev. 1.00 11 june 7, 2011 bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and the mcu is in idle or sleep mode, a falling edge on the rx input pin will through int pin wake-up the device. if this bit is equal to 0 and the mcu is in idle or sleep mode, any edge transitions on the rx pin will not wake-up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the receiver interrupt. if this bit is equal to 1 and when the receiver overrun flag oerr or receive data available flag rxif is set, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the oerr or rxif flags. bit 1 tiie : transmitter idle interrupt enable control 0: transmitter idle interrupt is disabled 1: transmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when the transmitter idle flag tidle is set, due to a transmitter idle condition, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the tidle flag. bit 0 teie : transmitter empty interrupt enable control 0: transmitter empty interrupt is disabled 1: transmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty flag txif is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the txif flag. ucr3 register the ucr3 register is the last of the uart control registers and controls the software reset operation. the only one available bit named urst in the uart control register ucr3 is the uart software reset control bit. when this bit is equal to 0 , the uart operates normally. if this bit is equal to 1 , the whole HT45B0F will be reset. when this situa- tion occurs, the transmitter and receiver will be reset. the uart registers including the status register and control registers will keep the por states shown in the above uart registers table after the reset condition occurs. bit76543210 name urst r/w r/w por 0 bit 7 urst : uart software reset 0: no action 1: uart reset occurs bit 6~0 unimplemented, read as 0
HT45B0F rev. 1.00 12 june 7, 2011 baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is deter - mined by two factors. the first of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to cal - culate the baud rate. the value n in the brg register which is used in the following baud rate calculation for - mula determines the division factor. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f [64 (n + 1)] clki f [16 (n + 1)] clki by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calcu- lated. calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = f [64 (n + 1)] clki re-arranging this equation gives n = f (brx64) clki 1 giving a value for n = 4000000 4800 64 () x 1 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br= 4000000 [64(12 + 1)] 4808 therefore the error is equal to = 0.16% " ( % ( * " ( % % " ( % % the following tables show the actual values of baud rate and error values for the two value of brgh. baud rate k/bps baud rates for brgh=0 f clki =4mhz f clki =3.579545mhz f clki =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 207 0.300 0.16 185 0.300 0.00 1.2 51 1.202 0.16 46 1.190 0.83 92 1.203 0.23 2.4 25 2.404 0.16 22 2.432 1.32 46 2.380 0.83 4.8 12 4.808 0.16 11 4.661 2.90 22 4.863 1.32 9.6 6 8.929 6.99 5 9.321 2.90 11 9.322 2.90 19.2 2 20.833 8.51 2 18.643 2.90 5 18.643 2.90 38.4 2 32.286 2.90 57.6 0 62.500 8.51 0 55.930 2.90 1 55.930 2.90 115.2 0 111.859 2.90 baud rates and error values for brgh 0
HT45B0F rev. 1.00 13 june 7, 2011 baud rate k/bps baud rates for brgh=1 f clki =4mhz f clki =3.579545mhz f clki =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 1.2 207 1.202 0.16 185 1.203 0.23 2.4 103 2.404 0.16 92 2.406 0.23 185 2.406 0.23 4.8 51 4.808 0.16 46 4.76 0.83 92 4.811 0.23 9.6 25 9.615 0.16 22 9.727 1.32 46 9.520 0.83 19.2 12 19.231 0.16 11 18.643 2.90 22 19.454 1.32 38.4 6 35.714 6.99 5 37.286 2.90 11 37.286 2.90 57.6 3 62.5 8.51 3 55.930 2.90 7 55.930 2.90 115.2 1 125 8.51 1 111.86 2.90 3 111.86 2.90 250 0 250 0 baud rates and error values for brgh 1 brg register bit76543210 name brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w porxxxxxxxx x : unknown bit 7~0 brg7~brg0: baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup.
HT45B0F rev. 1.00 14 june 7, 2011 uart setup and control for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, for - mat. this is composed of one start bit, eight or nine data bits and one or two stop bits. parity is supported by the uart hardware and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corre - sponding bno, prt, pren and stops bits in the ucr1 register. the baud rate used to transmit and re - ceive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received lsb first. although the transmitter and receiver of the uart are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart function is controlled using the uarten bit in the ucr1 regis - ter. if the uarten, txen and rxen bits are set, then these two uart pins will act as normal tx output pin and rx input pin respectively. if no data is being trans - mitted on the tx pin, then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and these two pins will be in the state of high im- pedance. when the uart function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. dis- abling the uart will also reset the enable control, the error and status flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the re - maining control bits in the ucr1, ucr2 and brg reg - isters will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defined above. if the uart is then sub - sequently re-enabled, it will restart again in the same configuration. data, parity and stop bit selection the format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9. the prt bit controls the choice if odd or even parity. the pren bit controls the parity on/off function. the stops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address detect mode con - trol bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 18001 17011 17101 example of 9-bit data formats 19001 18011 18101 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. * , , * % , * , * $ , * # , * " , * ! , * , * ' + * , - , . / * , * , , * % , * , * $ , * # , * " , * ! , * , * ' + * , - , . / * , , * (
HT45B0F rev. 1.00 15 june 7, 2011 uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is ob - tained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application pro - gram. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been trans - mitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other regis - ters, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmis - sion of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. how - ever, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data be- gins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to the high impedance state. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit lsb first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 regis - ter. the steps to initiate a data transfer can be sum - marized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the uart transmit - ter is enabled and the tx pin is used as a uart transmitter pin. access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be in - hibited from being written to the txr register. clearing the txif flag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif flag is set by the uart hardware and if set indicates that the txr register is empty and that other data can now be written into the txr regis - ter without overwriting the previous data. if the teie bit is set, then the txif flag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data trans - mission in progress, a write instruction to the txr reg - ister will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmitting break if the txbrk bit is set, then the break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13 n 0 bits, where n=1, 2, etc. if a break character is to be transmitted, then the txbrk bit must be first set by the application program and then cleared to generate the stop bits. transmitting a break character will not generate a transmit interrupt. note that a break condi - tion length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level, then the transmit - ter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized.
HT45B0F rev. 1.00 16 june 7, 2011 uart receiver the uart is capable of receiving word lengths of ei - ther 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, will be stored in the rx8 bit in the ucr1 register. at the receiver core lies the receiver shift register more commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recov - ery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the re - ceive data register, if the register is empty. the data which is received on the external rx input pin is sam - pled three times by a majority detect circuit to deter - mine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin to the shift register, with the least significant bit lsb first. the rxr register is a four byte deep fifo data buffer, where four bytes can be held in the fifo while the 5th byte can continue to be received. note that the appli- cation program must ensure that the data is read from rxr before the 5th byte has been completely shifted in, otherwise the 5th byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summa- rized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart re - ceiver pin. at this point the receiver will be enabled which will be - gin to look for a start bit. when a character is received, the following sequence of events will occur: the rxif bit in the usr register will be set then rxr register has data available, at least three more character can be read. when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. if during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. the rxif bit can be cleared using the following soft - ware sequence: 1. a usr register access 2. a rxr register read execution receiving break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as specified by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has re - ceived a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is re - garded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are received. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the fol- lowing: the framing error flag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif flags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the read - ing of a stop bit, the receiver status flag in the usr register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt flag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1.
HT45B0F rev. 1.00 17 june 7, 2011 managing receiver errors several types of reception errors can occur within the uart module, the following section describes the vari - ous types and how they are managed by the uart. overrun error oerr flag the rxr register is composed of a four byte deep fifo data buffer, where four bytes can be held in the fifo register, while a 5th byte can continue to be re - ceived. before the 5th byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the follow - ing will happen: the oerr flag in the usr register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr register followed by a read to the rxr register. noise error nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame, the following will occur: the read only noise flag, nf, in the usr register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register. no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr register read operation followed by an rxr register read operation. framing error ferr flag the read only framing error flag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high. otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared in any reset. parity error perr flag the read only parity error flag, perr, in the usr reg - ister, is set if the parity of the received word is incor - rect. this error flag is only applicable if the parity function is enabled, pren=1, and if the parity type, odd or even, is selected. the read only perr flag is buffered along with the received data bytes. it is cleared on any reset, it should be noted that the ferr and perr flags are buffered along with the corre - sponding word and should be read before reading the data word. uart interrupt structure several individual uart conditions can generate a uart interrupt. when these conditions exist, a low pulse will be generated on the int line to get the atten - tion of the microcontroller. these conditions are a trans - mitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its correspond - ing interrupt vector where it can be serviced before re - turning to the main program. four of these conditions have the corresponding usr register flags which will generate a uart interrupt if its associated interrupt en - able control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corre - sponding enable control bits, while the two receiver in - terrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart in - terrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect con - dition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a falling edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay, com- monly known as the system start-up time, for the oscil- lator to restart and stabilize before the system resumes normal operation. note that the usr register flags are read only and can - not be cleared or set by the application program, neither will they be cleared when the program jumps to the cor - responding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart regis - ter section. the overall uart interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed.
HT45B0F rev. 1.00 18 june 7, 2011 address detect mode setting the address detect function enable control bit, adden, in the ucr2 register, enables this special function. if this bit is set to 1 , then an additional qual- ifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is equal to 1 , then when the data is available, an interrupt will only be gener- ated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit of the microcontroller must also be enabled for correct interrupt generation. the highest address bit is the 9th bit if the bit bno=1 or the 8th bit if the bit bno=0. if the highest bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is equal to 0 , then a receive data available interrupt will be generated each time the rxif flag is set, irre - spective of the data last but status. the address de - tect and parity functions are mutually exclusive functions. therefore if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit pren to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0x 1 adden bit function power-down and wake-up the mcu and device are powered down independently of each other. the method of powering down the mcu is covered in the previous mcu section of the datasheet. the device must be powered down before the mcu is powered down. this is implemented by first clearing the uarten bit in the ucr1 register to disable the uart module circuitry after which the scs internal line can be set high to disable the spi interface circuits. when the uart and spi interfaces are powered down, the sck and clki clock sources to the device will be disabled. the device can be powered up by the mcu by first clearing the scs line to zero and then setting the uarten bit. if the uart circuits is powered down while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the uart circuits is powered down while receiving data, then the reception of data will likewise be terminated. when the uart circuits is powered down, note that the usr, ucr1, ucr2, ucr3, transmit and receive regis - ters, as well as the brg register will not be affected. the device contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit named uarten, the receiver enable bit named rxen and the receiver interrupt enable bit named rie, are all set before the mcu and device are powered down, then a falling edge on the rx pin will wake up the mcu from its power down condition. note that as it takes a certain period of time known as the system start-up time for oscillator to restart and stabilize after a wake-up, any data received during this time on the rx pin will be ig - * 0 1
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application circuit HT45B0F rev. 1.00 19 june 7, 2011
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1 5 ) * + nored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up enable control and receive inter - rupt enable control being set, the global interrupt enable control and the related interrupt enable control bits must also be set. if these two bits are not set, then only a wake-up event will occur and no interrupt will be ser - viced. note also that as it takes a period of delay after a wake-up before normal microcontroller resumes, the relevant uart interrupt will not be serviced until this pe - riod of delay time has elapsed.
package information 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.402 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.21 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 08 HT45B0F rev. 1.00 20 june 7, 2011 & ( , 3 4 : ;
product tape and reel specifications reel dimensions 16-pin nsop (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 HT45B0F rev. 1.00 21 june 7, 2011 ,

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carrier tape dimensions 16-pin nsop (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT45B0F rev. 1.00 22 june 7, 2011 . 8 . . % 3 4 % , % % * + ) 0 * + * * * < * * < 1 * * * < * 1 2 * 1 = * :
HT45B0F rev. 1.00 23 june 7, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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